1. Field
The embodiments disclosed herein relate to a delay locked loop circuit, and more particularly, to a delay locked loop circuit including a delay line capable of delaying an input clock signal by a predetermined amount of delay so as to reduce sensitivity to variations in PVT (process, voltage, and/or temperature), and a synchronous semiconductor memory device including the same.
2. Description of the Related Art
In recent years, the speed and the degree of integration of dynamic random access memories generally used as the main memories of electronic systems have increased in order to meet user demands.
The dynamic random access memory device is a volatile memory having memory cells each of which has one access transistor and one storage capacitor as a unit memory cell, and has a refresh operation in addition to read and write operations.
High-performance DRAMs with an improved operation speed, such as a SDRAM (synchronous DRAM), a DDR SDRAM (double data rate SDRAM), and an FCRAM (fast cycle RAM), have been developed in this field. Among them, conventional SDRAM can input or output data at either the rising or falling edges of a clock signal. Meanwhile, the DDR SDRAM can input or output data at both the rising and falling edges of a clock signal. Therefore, the data transmission rate of the DDR SDRAM is two times that of a conventional SDRAM.
For example, when a memory system is operated at 400 MHz and transmits data at the rising and falling edges of a clock signal, a valid data transmission rate to one pin per second is 800 Mb/s. In this case, a data bit time is 1.25 ns, which is very short. In order to meet these timing requirements, it may be necessary to provide a circuit that matches the phase of an external system clock with the phase of an internal on-chip clock in an interface circuit.
When a clock that is input from the outside is used inside the circuit, clock skew occurs by the internal circuit, which may cause the external system clock signal and internal on-chip clock signal to be out of phase. A delay locked loop (DLL) is used to compensate the clock skew such that the phase of the internal clock signal is equal to the phase of the external clock signal. That is, the delay locked loop controls the time delay occurring when the clock input from the outside is used inside the circuit such that the phase of the internal clock signal is equal to that of the external clock signal.
The delay locked loop generally used in the high-performance DRAMs generates an internal clock signal whose phase is synchronized with that of the external clock signal (i.e., delayed and locked with respect to the external clock). As such, the internal clock signal is used as a signal for controlling data output timing.
As the operation frequency of an electronic system or a semiconductor memory device used in the electronic system has increased, the frequency range covered by the delay locked loop (hereinafter, referred to as “DLL”) has been extended from a low frequency of 400 MHz to a high frequency of 1.6 GHz. That is, since a DLL circuit is used for a DDR memory in order to synchronize an internal clock with an external clock, the DLL circuit needs to satisfy a wide operation speed range required for present day commercial DRAM (DDR2: 400 MHz to 800 MHz, DDR3: 800 MHz to 1600 MHz).
In addition, the DLL circuit needs to have a wide delay range in order to exactly synchronize data with a clock even though a surrounding environment and a manufacturing process vary. In order to improve the operation speed in a semiconductor device, a DLL circuit may be used to meet requirements for fine delay adjustment.
The DLL circuits may be mainly classified into an analog DLL circuit and a digital DLL circuit. The analog DLL circuit uses an analog delay line to form a delay cell that is only slightly, if at all, sensitive to PVT changes. Therefore, it is possible to calculate the predictable total amount of delay. As a result, it is possible to use the analog DLL circuit while limiting the number of delay cells according to operation frequency ranges. However, since a bias circuit for driving an analog cell and other circuits are used in the analog DLL circuit, a relatively long wake-up time is required, and a large amount of current is consumed in the non-operation state of the DRAM.
Meanwhile, a digital DLL circuit has a relatively short wake-up time and hardly consumes a current in the non-operation state. However, in the digital DLL circuit, each delay cell including, for example, an inverter, has a significantly large response variation due to changes in PVT, and a large number of delay cells are required. In addition, the digital DLL circuit consumes a large amount of power during an operation.
Therefore, a delay line capable of stably performing a delay operation by a predetermined amount of delay with reduced sensitive to a variation in PVT would be desirable in a delay locked loop circuit.